搜索资源列表
fifo程序
- 用verilog语言在fpga中实现fifo功能！-using Verilog language in which they simply realize fifo function!
fifo
- 使用Verilog语言编写，把FPGA配置成一个fifo
用verilog写的对ad0809的控制
- 用verilog写的对ad0809的控制，完整工程，希望对大家能有帮助,Written using Verilog for ad0809 control, complete works, in the hope that we can help
cy7c68013工作在SLAVE FIFO下的FPGA源代码
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写,cy7c68013 slave fifo mode code ,written by hard ware language
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
sfifo
- verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
FIFO
- 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
fifo
- FPGA Verilog语言编写的fifo模块-The fifo module of FPGA Verilog language
带FIFO的ov7670 FPGA应用程序，经测试可用
- 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
sp6ex19
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
eetop.cn_FIFO_Buffer
- 异步FIFO的Verilog程序及其测试程序(FPGA/Verilog FIFO_ASYN)
tx_interface_project
- 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
FIFO
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA FIFO example, reading and writing FIFO in FPGA chip.)
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
fifo
- Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
通信协议FPGA
- 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface